http://www.vlsichipdesign.com News/Views/Blog/Forum/Jobs/Technical Know How's/Frequently Asked Interview Questions about VLSI Chip Design en-us http://www.vlsichipdesign.com/online_verilog_code.html If you are new to the VLSI chip design industry or want to learn verilog easily or in a situation to code verilog for your design and need verilog codes online, this Article is the right choice then, discusses about verilog codes for flip-flops/comparator/subtractor/multiplier/multiplexer/.... http://chipdesignart.wordpress.com/2008/04/21/types-library-cells-to-suite-different-implementation-needs/ We notice different standard cells in our library... why do we really need to have so much of standard cells . This Article discusses about the types of standard cells and for what it is in need for? Check this article http://chipdesignart.wordpress.com/2008/03/27/nor-flash-vs-nand-flash-comparison/ Articles discusses about NAND flash and NOR flash ,across various parameters which will aid in chip-level decision making process http://chipdesignart.wordpress.com/2008/02/21/static-timing-analysis-mock-interview-part-4/ Really Wonderful Article, which when browsing will give a feeling of being a part of an Static Timing Analysis Interview Panel [Silent Listener Role], where in an STA Expert is getting Interviewed , questions addressing on Chip variations, how about modelling OCV effects, what are the various causes of OCV, what does CRPR[common re-convergence pessimism Removal], Even if you are not from Static Timing Analysis Area of Expertise, will be good to know the concepts, and if you are prepared or planned for an interview would surely give an insight what would be expected from YOU to be a part of "On-board" http://www.vlsichipdesign.com/knowledgehome.html A Collection of a Designers Experience in his profession of Chip Designing, lot of technical articles related to Chip Designing, surely help to be an edge in your technical skills, and viewing this link will surely help you to learn new concepts which will aid in first pass silicon success dear Designer, so why not just trust me and give a click and if you dont like do let me know @ vlsichipdesigner@gmail.com, I guarantee you will surely learn and the best part is all the information is for free http://www.vlsichipdesign.com/static_timing_analysis.html This article clearly explains the concepts of static timing analysis, with lots of diagrams, surely understand the concepts behind scenario's which causes false paths, multicycle paths, how to time Source synchronous paths, incase of Memory timing's and many more. It will helpful resource both for a novice Engineer as well as an Experienced engineer to brush up. http://chipdesignart.wordpress.com/2007/12/28/static-timing-analysis-mock-interview/ This is just a mock interview : An Timing engineer claiming mastery in Static Timing Analysis is coming for an Interview. Interviewer: Welcome Job Seeker: thanks (aliasing I for Interviewer and J for Job-seeker) I : In your resume you had mentioned that are an expert in STA(Static Timing Analysis), how comfortable are you. J: Good comfortable. I : one basic question, what is STA. J : STA stands for Static Timing Analysis, checks whether the Design Meeets the timing requirements, across all the timing arcs. I : You mentioned timing Checks , what do you mean by that. J : Setup Timing Check, Hold Timing Check, Clock-gating Check I : Good, do you perform some checks for asynchronous stuffs or not. J : Yes , I do perform checks , like recovery, removal. I : what is recovery and removal check? J : recovery is similar to setup check and removal is similar to a hold check. I : what are the various Timing-paths you see in any chip? J : Path 1: Path starting from input port and ending at a Register Data Path 2: Path starting from register output and ending at the register output Path 3: Path starting from register output and ending at the output port Path 4: Path starting from inputport and ending at the output port. Path 5: Timing Source synchronous paths. I : Good, have you come across with a report “check_timing “, does this was of some use to you any-time. J : yes , as soon as i recieve database , i used to generate this report, this will guide me to know the list of flip-flops not having clocks, flip flops with multiple clocks, input port constraints missing, timing loops and things like that , It is a quiet informative report. I : We will continue after a break, signoff for now…. continue in part 2 section. Till then To brush up the basics of Static Timing Analysis: http://www.vlsichipdesign.com/static_timing_analysis.html http://www.vlsichipdesign.com/asic_vlsi_faq/faq_page1.html Detailed frequently asked interview questions good part with answers available more than 30 pages for your reference. All the Very Best http://www.vlsichipdesign.com/semiconductor_patent.html Collection of latest Semiconductor related patents http://www.vlsichipdesign.com/asiccompaniesinindia_page1.html List of VLSI related Design companies in INDIA. This really could help the designers to know the companies and where to apply in case if they are in search of jobs , a quick ready-reckoner http://www.vlsichipdesign.com/H1B_visa.html This article will help to know the process involved in H1B processing , documents required and things like that, this article comes with a disclaimer, for correct information check only the US Government website, this is just as an educational awareness of the information http://www.vlsichipdesign.com/askyourselfarchitect.html A wonderful article, which will give you a virtual feeling as if you were a chief Architect for a Chip and you need to decide on the architecture what alll will you think on it to make it happenn my dear designer http://www.vlsichipdesign.com/vlsidesignflow.html Are you new to ASIC Design and want to know the ASIC chip design flow , starting from scribling in Desk bench regarding a concept to chip design in a silicon, a complete flow is well designed and structured and can be used as a reference flow to understand the concepts http://chipdesignart.wordpress.com/2007/09/07/thoughts-of-an-good-rtl-designer/ I have been designing RTL for years or new to RTL designing what all i take care while writing RTL say from Linting, how to write power-compiler friendly, DFT friendly, Tester friendly and so on... http://chipdesignart.wordpress.com/2007/12/13/gate-level-simulation-mock-interview/ A mock interview is conducted from a Verification engineer who is claiming he is in mastery in Gate-level simulation is coming for an Interview, Interviewer is asking questions, this Article takes us to stream of Questions and Answers a place of Virtually alive in an Interview Hall..