Verilog code sample for shiftregister.

module shift (Clk, Shift_in, Shift_out);
input Clk,Shift_in;
output Shift_out;
reg [7:0] tmp;

always @(posedge Clk)
begin
tmp = tmp << 1;
tmp[0] = Shift_in;
end
assign Shift_out = tmp[7];
endmodule

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