Verilog code sample for decoder.

module decoder (sel, result);
input [2:0] sel;
output [7:0] result;
reg [7:0] result;

always @(sel or result)
begin
case (sel)
3'b000 : result = 8'b00000001;
3'b001 : result = 8'b00000010;
3'b010 : result = 8'b00000100;
3'b011 : result = 8'b00001000;
3'b100 : result = 8'b00010000;
3'b101 : result = 8'b00100000;
3'b110 : result = 8'b01000000;
default : result = 8'b10000000;
endcase
end
endmodule

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