Verilog code sample for counter.

module counter (Clk, CLR, Q_out);
input Clk, CLR;
output [3:0] Q_out;
reg [3:0] temp;

always @(posedge Clk or posedge CLR)
begin
if (CLR)
temp = 4'b0000;
else
temp = temp + 1'b1;
end
assign Q_out = temp;
endmodule

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