Verilog code sample for 8bit adder with carry input.

module 8bitadder_carryinput(A, B, Carry_in, SUM);
input [7:0] A;
input [7:0] B;
input Carry_in;
output [7:0] SUM;

assign SUM = A + B + Carry_in;
endmodule

People found these links also interested and knowledgeable

Register Transfer Language Discussions

• Good verilog coding styles
• Thoughts of an Good RTL designer