asic synthesis

#### Now, let us know the Test Part of the Design

set test_default_period 100

set test_default_delay 5

set test_default_bidir_delay 30

set test_default_strobe 35

set test_default_strobe_width 0

#### Specify that there is no scan-chain present in the design

set_scan_configuration -existing_scan false

#### specify whether clock mixing is allowed or not while scanstitching

set_scan_configuration -clock_mixing no_mix

#### specify the style of flip-flop

set_scan_configuration -style multiplexed_flip_flop

#### Specify the scanchain methodology whether full-scan or partial scan

set_scan_configuration -methodology full_scan

#### Specify the longest chain length according to the tester memory

set_scan_configuration -longest_chain_length 200

#### Specify the scan-enable signal

set_scan_signal test_scan_enable -port <design_scan enable port name>

#### Specify a case analysis value for to the tool to be in the scan-mode while scan-stitching

set_test_hold <value either 0/1> <design scan-mode port name>

#### Specify the designs for which scan-stitching is not required

set_scan_element false [get_designs <sub design_name>

#### Specify the scan-in and scan-out port of the design to the tool

set_scan_signal test_scan_in -port [get_ports <design scan_port input>

set_scan_signal test_scan_out -port [get_ports <design scan_port out-put>

#### specify the test-clock in the design

create_test_clock < clock_name> -period < specify period numeric> -waveform {rise-edge fall-edge}

#### run the check-test to know the design violations w.r.t. test

check_test -verbose

##### command to insert scan

insert_scan -map_effort high

#### Report generation

report_test -scan_path ### command to list all the scan-chains

#### Save the database

write -f db -h -o <design_name_scan.db>

#### Set some variables for proper saving of verilog netlist file

set verilogout_no_tri true

set bus_naming_style [format "%s%s" "%s\[" "%d\"]

write -f verilog -h -o <design_name_scan.v>

###Report Generation after scan-insertion

report_constraints -all_violators -verbose ### Command to report all the violations

report_area ### command to report the design area

report_reference ### command to report the design details as per the sub-blocks

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.