asic synthesis

### To constrain purely combinational paths

set_max_delay <specify delay values> -from <source path> -to <destination path>

### For the high fanout nets for which tree will be built and to get away from false loading violation

set_ideal_net <reset_name>

set_ideal_net <scan_enable_name>

### In-order to constrain specific paths passing through the muxes, for example for the tool to

### concentrate on the functional-paths , specify case_analysis for functional paths.

set_case_analysis <case value 0/1> <Mux/Bi-furcating paths>

#### If the design requirement is for area critical designs

set_max_area 0

#### To prevent the tool from optimizing

#set_dont_touch <area to be dont-touched>

####Mapping the RTL specific to the Targetted Technology Library

#### The command means to map it , with scannable flop's, with high optimization possible,

#### Area optimized for non-critical-paths as-well-as boundary paths optimized.

compile -scan -map_effort high -area_effort high -boundary_optimization

#### Save the database

write -f db -h -o <design_name.db>

#### Set some variables for proper saving of verilog netlist file

set verilogout_no_tri true

set bus_naming_style [format "%s%s" "%s\[" "%d\"]

write -f verilog -h -o <design_name.v>

### Save the Used SDC(Synopsys Design Constraints file>

write_sdc <design_name.sdc>

###Report Generation

report_constraints -all_violators -verbose ### Command to report all the violations

report_area ### command to report the design area

report_reference ### command to report the design details as per the sub-blocks

### A very powerful command to know the quality of the design constraints

check_design ###Command to know the design <for example flops which are not getting clocks, ports which are not constrained>

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.