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asic synthesis |
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####Specify the Clocks in the Design ###### #### Example for one Clock in the Design named clock1 create_clock -period $clock1_period -waveform [list 0 $clock1_period_half ] -name $clock1_name <specify the location of the node where clock need to be generated> set_clock_skew -ideal -uncertainty $CTS_clock1_skew $clock1_name set_clock_transition 0.3 $clock1_name set_clock_latency $clock1_latency_number $clock1_name set_dont_touch_network $clock1_name #### Generate the same list of constraints for all the clocks in the design #### Generate the False and Multi-cycle paths in the design as Timing Exceptions for the tool. #### False And Multi-cycle paths are purely Design Specific. #set_false_path -from <Source > -to <Destination> -setup #set_false_path -from <Source > -to <Destination> -hold #set_multicycle_path <no of cycles> -from <source> -to <destination>
##### Steps to constrain the inputs/outputs and the design set_input_transition $clock1_period_onetenth [all_inputs] set_max_transition $clock1_period_onetwenth $current_design #### Specify the wire-load model set auto_wire_load_selection true ### Tool automatically selects the wire-load model #### Create virtual clocks to constrain the ports.To understand concept behind the virtual clocks #### Check out the ASIC FAQ's column. #### To constrain inputs set_input_delay <input delay value> -clock <with respect to virtual clock> <input_port1> ### Similar way define for all the inputs and w.r.t virtual clocks #### To constrain out-puts set_output_delay <output delay value> -clock <with respect to virtual clock> <output_port1> ### Similar way define for all the outputs and w.r.t virtual clocks Synopsys constraints continued in page 3 About Synopsys |
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