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static timing analysis mock interview in part 4


I : welcome back...

J : thanks sire

I : can we sign-off in the Static Timing Analysis tool, with the real operating frequency or do you see any reason we need to have some extra margins.

J : Sir, we can close with the real operating frequency itself, but un-fortunately there are so much variations.

I : what do you mean by variations?

J : Die to Die there will be variations, Wafer to Wafer there will be Variations, lot to lot there will be variations, Package variations, on chip variations sir.

I : What do you mean by on-chip variations.

J : with in the chip itself, there are so many things which can cause Timing Variations, or Timing uncertanities Sir, like

  • IR Drop related Timing Variation
  • Channel length Variation
  • temperature variations
to name a few...

I : good, do you really account it in your STA analysis or just leave it God .

J : We live in a technical world, when we know there can be an issue, we cannot leave it for chance and more over huge money is involved Sir, there are ways to take care in STA sir.

I : I like your attitude. let me know how will you do this.

J : Sir, I had used primetime for my STA analysis and there are concepts for OCV[on-chip variation] , we used to use Derate methodology.

I : what is this Derate methodology you are referring too?

J : what i meant was there are some commands like "set_timing_derate" , which can be used in the cell and for the net , for the clock path, for the Data path and OCV effects can be modelled and Analyzed and Qualified Sir.

I : Very Good. You know the practical aspects.

J : thanks sir.
I : we will connect later...
Jobseekers: To know more about On-chip Variation

http://www.vlsichipdesign.com/ocv.html
earlier Interview sessions about STA:
I : we will connect later, I need to catch up for a meeting.

Meanwhile, Job-seeker, if you want to brush up, open your book and read, dont waste your time, "Life is all about Timing Optimization & Optimal Utilization, similar is Chip design "

http://www.vlsichipdesign.com/static_timing_analysis.html
earlier Interview sessions about STA:

Part I :

STA mock interview part 1

Part II:

STA mock interview part 2
Part 3:

STA mock interview part 2
Till then To brush up the basics of Static Timing Analysis:

http://www.vlsichipdesign.com/static_timing_analysis.html


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