I [Interviewer] : Is the Timing analysis intelligent enough to know all the clocks and generated clocks in your design .

J [job seeker] : We used to create the clock definitions, Generated clock definitions using their specific master clocks , clocks specifing their rise and fall edges, periods and things like that..

I : Well, What is this ideal mode and propagated mode in clocks.

J : Ideal mode is assuming that the clocks to all the flops are assumed to be reaching at the same time. This is used during synthesis stage, assuming we are going to perform clock-tree synthesis and then we will notice the real time clock arrival times.

In the propagation mode settings are used after CTS[clock tree synthesis] is performed, and after this stage while we perform the Static Timing Analysis, we need to set this.

I : Assume i forgot to be in the propagation mode after CTS, and i had performed STA, do you still see any risk.

J : The Chip timing performance is totally not guaranteed after the Silicon. Because we are blindly assuming that the Clock-tree synthesis has performed a Great job and not validating the realistic behaviour of the Clocks. Atleast i would not do this.

I : good , Very Good.

I : what is the term clock - uncertanity and why we need this, do you see a reason.
J : There are so much uncertanity in clocks, like clock jitter and there could be lot of variations: clock variations, process variations , so some extra margin is required and it is modeled with uncertainity term.

I: Good , can i specify different uncertanity value for setup as well as hold.

J : Yes sire, there are provisions to do this, there are specific switches specific for setup and hold requirement.

I : we will connect later, I need to catch up for a meeting.

Meanwhile, Job-seeker, if you want to brush up, open your book and read, dont waste your time, "Life is all about Timing Optimization & Optimal Utilization, similar is Chip design "


earlier Interview sessions about STA:

Part I :

STA mock interview part 1

Part II:

STA mock interview part 2
Part 3:

STA mock interview part 3
Part 4:

STA mock interview part 4
Till then To brush up the basics of Static Timing Analysis:

http://www.vlsichipdesign.com/static_timing_analysis.html