On Chip Variations or inter-die variations could be caused due to

• IR drop
• Vt variations
• Channel length variation

So the normal flow of qualifying the Timing with plain worst and best corners is no more enough.

To account for this variations need to account an inbuilt pessimism by derating the paths thereby the cells will perform to be slower and then validate the design behaviour and qualifying upfront .

Lets understand to model the OCV in STA

Concept behind Setup Derate in STA

Concept behind hold Derate in STA

On chip Variation with CRPR