- $x loss, if a bug found before packaging
- $10x loss, if a bug found, after packaging
- $100x loss, if a bug found, in a System
- $1000x loss, if a bug found, in the field
Goal of DFT: - To catch the Manufacturability problems and to deliver only Good die to the customer.
- Reduce Test Costs
What are the various Test? - Exhaustive Tests - Covers all the possible test vectors
- Functional Tests - Covers the functionality of the Chip
- Fault Modelled - Covers the potential manufacturability problems
Mantra of DFT : Controllability and Observability Controllability: Ability to control the internal nodes using primary inputs Observability: Ability to observe the changes at the internal nodes using primary outputs. DFT Strategy(what all to be covered) - Boundary Scan Tests
- Logic BIST simulations
- Memory BIST simulations
- Tester specific vector generation and simulations
- Tester vector compression techniques to reduce tester time
- At-speed testing mechanism's
- Scan-shift and scan-capture methodologies
- IDDQ testing
- Wafer Level Burn-in Tests to know Known Good Dies(KGD)
- Wire pull tests
- DC parameter tests
- AC parameter tests
- Path-delay tests
- Delay tests
- Transition fault testing
Metric to measure DFT Fault Coverage = 100 X [Number of Detected faults/Total number of faults in the Design]
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