#### Now, let us know the Test Part of the Design

set test_default_period 100

set test_default_delay 5

set test_default_bidir_delay 30

set test_default_strobe 35

set test_default_strobe_width 0

#### Specify that there is no scan-chain present in the design

set_scan_configuration -existing_scan false

#### specify whether clock mixing is allowed or not while scanstitching

set_scan_configuration -clock_mixing no_mix

#### specify the style of flip-flop

set_scan_configuration -style multiplexed_flip_flop

#### Specify the scanchain methodology whether full-scan or partial scan

set_scan_configuration -methodology full_scan

#### Specify the longest chain length according to the tester memory

set_scan_configuration -longest_chain_length 200

#### Specify the scan-enable signal

set_scan_signal test_scan_enable -port

#### Specify a case analysis value for to the tool to be in the scan-mode while scan-stitching

set_test_hold

#### Specify the designs for which scan-stitching is not required

set_scan_element false [get_designs

_{#### Specify the scan-in and scan-out port of the design to the tool}

_{set_scan_signal test_scan_in -port [get_ports}

_{set_scan_signal test_scan_out -port [get_ports}

_{#### specify the test-clock in the design}

_{create_test_clock -period -waveform {rise-edge fall-edge}}

_{#### run the check-test to know the design violations w.r.t. test}

_{check_test -verbose}

_{##### command to insert scan}

_{insert_scan -map_effort high}

_{#### Report generation}

_{report_test -scan_path ### command to list all the scan-chains}

_{#### Save the database}

_{write -f db -h -o}

_{#### Set some variables for proper saving of verilog netlist file}

_{set verilogout_no_tri true}

_{set bus_naming_style [format "%s%s" "%s\[" "%d\"]}

_{write -f verilog -h -o}

_{###Report Generation after scan-insertion}

_{report_constraints -all_violators -verbose ### Command to report all the violations}

_{report_area ### command to report the design area}

_{report_reference ### command to report the design details as per the sub-blocks}

_{About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.}