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Synopsys Synthesis Constraints Template ###Customize according to your Design needs ######################################################## #### Portion to Edit #### Variables clock1_name is the Clock name, clock1_period is the Clock period, #### clock1_period_half is the half of the clock period #### set clock1_name #### set clock1_period #### set clock1_period_half [expr $clock1_period / 2] #### set clock1_period_onetenth [expr $clock1_period / 10] #### set clock1_period_onetwenth [expr $clock1_period / 20] #### set clock1_latency #### set CTS_clock1_skew ######################################################## #### Source the .synopsys_dc_setup file, File which has all the library settings source .synopsys_dc_setup #### Read the rtl files read_verilog ### Similar way read all the RTL files ### Specify the Top-level file name current_design #### Link the design link #### Uniquify the design, for designs with multiple instantiation uniquify #### Design Constraints following.... Synopsys constraints continued in page 2 About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.
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