|
In this article, will discuss about
* what is crosstalk * Crosstalk role for Signal Integrity. * Mechanism to verify the impact of Crosstalk in Chip design flow. * Precautionary Measures to reduce Crosstalk in Chip Design Flow.
Crosstalk: As the name signifies, crosstalk is a behaviour in which the electrical disturbances caused due to action of the neighbour nets, in the world of interconnect arena. Shrinking geometries and more gate densities, has brought in wire interconnections very close by, thereby increasing the cross-coupling capacitance across nets, as-well reduced� parasitic capacitances to the substrates.
Impacts of Crosstalk to Signal Integrity:
* Crosstalk Delay
* Crosstalk Noise
Crosstalk Delay: Crosstalk affects the behaviour of signal delays , when the neighbour nets are switching and they are present in very close proximity. When the neighbour nets are switching in the same direction which makes the interconnect net to be faster causing hold violation. When the neighbour nets are switching in the�opposite direction which makes the interconnect net to beslower causing�setup violation.
Crosstalk noise:
Crosstalk noise plays a role, across a static net(constant net) and a high frequency switching net. When there is a transition in the high-frequency switching net, which inturn causes a voltage bump and creates a transition in the constant net and if the transitioned value is captured then this glitch can cause a functional failure.
Mechanism to verify Impact of Crosstalk in Chip Design Flow * Ensure that the Extracted parasitic SPEF file is with coupling capacitance enabled.
* Enable SI feature in the Primetime
* Read the parasitics in the Primetime SI tool with -keep_coupling_capacitance switch, so that the tool preserves the coupling cap values
* Based on the Technology specify the Crosstalk filters,
Precautionary Measures to reduce Crosstalk in Chip Design Flow * Ensure that the high-frequency nets are shielded
* Ensure that the clock is routed with Double width triple spacing
* set the maximum length for the nets so that you dont see long nets running across in the design
* Honour Transition/Slew during synthesis and Placement and routing stages , so that no low driving cells present
* For the high-frequency nets increase the spacing across the nets, which will reduce the impact of Cross-talk
Primetime, Primetime SI is a trademark of Synopsys Inc
About Synopsys Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.
|
