Recieve free answers for interview questions, by referring 10 email ids of your friends to vlsichipdesigner@gmail.com
Vlsichipdesign
Home
Faq Page5 PDF Print E-mail
User Rating: / 0
PoorBest 

11. What is metastability and steps to prevent it.

Metastability is an unknown state it is neither Zero nor One.Metastability happens for the design systems violating setup or hole time requirements. Setup time is a requirement , that the data has to be stable before the clock-edge and hold time is a requirement , that the data has to be stable after the clock-edge. The potential violation of the setup and hold violation can happen when the data is purely asynchronous and clocked synchronously.

Steps to prevent Metastability.

1. Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain. Using Synchronizers, recovers from the metastable event.

2. Use synchronizers between cross-clocking domains to reduce the possibility from metastability.

3. Using Faster flip-flops (which has narrower Metastable Window).

12. what is local-skew, global-skew,useful-skew mean?

Local skew : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.

Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.

Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

related information. asic and vlsi frequently asked interview questions continued in page 6

Comments

Show/Hide Comment form
 
 

Google translate

Browse this website in: