35. What are the various ways to reduce Clock Insertion Delay in the Design

1. Number of Clock sinks
2. Balancing two different clock frequencies
3. Placement of clock sinks.
4. Placement of Clock gating cells
5. Clock tree buffers/inverters drive strength's
6. Clock Transition
7. placement of Clockgating cells and the clock sinks
8. Combinationals cells in the path of clocks (say clock dividers, muxes, clockgates) ...

36. what are the various functional verification methodologies

• TLM(Transaction Level Modelling)
• Linting
• RTL Simulation ( Enivronment involving : stimulus generators, monitors, response checkers, transactors)
• Gate level Simulation
• Mixed-signal simulations
• Regression