31. what are the measures in the Design taken for Meeting Signal-integrity targets

As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let's see now by what are all the measures we can reduce/solve it.

• As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing.
• In-case of SI violation, spacing the signal nets reduces cross-talk impacts.
• Shield the nets with power-nets for high frequency signal nets to prevent from SI.
• Enable SI aware routing , so that the tool takes care for SI
• Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements
• Route signals on different layers orthogonal to each other
• Minimize the parallel run-length wires, by inserting buffers.

32. what are the measures taken in the Design achieving better Yield

Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranting the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge.

• Create more powerful stringent runset files with pessimistic spacing/short rules.
• Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it.
• For via-reliability issues, use redundant vias, to reduce the chances for via-breakage.
• In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories.
• Optimal placing of de-coupling capacitances, reduces the power-surges.
• Doubling the width of the non-critical nets, clock-nets can increase the yield parameter.
• Ensure that the poly-orientation are maintained.