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29. what are the measures to be taken to design for optimized area As silicon real-estate is very costly and saving is directly propotional to the company's revenue generation lot of emphasize is to design which has optimial utilization in the area-front. The steps to reduce area are - If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area.
- Abut the VDD rows
- Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets.
30. what all will you be thinking while performing floorplan - Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length.
- Minimize the usuage of blocks other-than square shapes, having notches
- Place the blocks based on accessibility/connectivity, thereby reducing wire-length.
- Abut the memory, if the pins are one-sided, there-by area could be reduced.
- If the memory communicates to the outside world more frequently , then placing at the boundary makes much of a sense.
- Study the number of pins to be routed, with the minimum metal width allowed , estimate the routability issues.
- Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise.
related information. asic and vlsi frequently asked interview questions continued in page 15
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