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27. what is meant by Library Characterizing: "Chip designing is all about Modeling the silicon", and how well we characterize the silicon, is all the game. So initially let us assume our process technology is say "32nm", for example: Now we need to develop a test-chip, having modules (digital & analog), and study our silicon timings. Now the toughest job is to generate library views(formats specific to each tool understandable formats).There is a bit of timing in accuracy possible in the views across the formats. 28. what is meant by wireload model: In the synthesis tool, in order to model the wires we use a concept called as "Wireload models", Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanin then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available related information. asic and vlsi frequently asked interview questions continued in page 14
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