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This article explains the thought process to guide before estimating the Die-size of a Chip. - Make a List of the Intellectual Property and their corresponding Area count
- What is the Manufacturing Process Targetted
- Is the chip pad limited or core limited
- What is the utilization factor targeted
- What is the total memory area in the chip
- What is the package requirement (Flipchip/Wirebond)
- Preparation of Padring based on the Interface requirements
- What is the estimated gatecount per sq mm2 in the specific process
- What is the total Chip area
- Derive X & Y co-ordinates of the Chip
- What is the area for scribe-line
Related Articles: Optimal Padring Design and Essentials in any Padring
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Comments
For a core limited design,the die size of the chip is estimated by calculating the area of standard cells, macros, and % estimate of area for routing and other miscelenious operations.
Miscelenious operations inlude end cap and dg cap insertion, Definite blockages needed, % estimate for the cts and optimizations. These figures are generally estimated from the previous design.
For a pad limited design, the die size is estimated by calculating the perimeter needed for placing the pads.