clock tree constraints : Layout Requirement Specification
what all need to be communicated to the person who builds the clock tree's. He need to aware of the complete information otherwise we will see surprises on timing after clock-tree synthesis has happenned or timing convergence will take a lot of time. - first and foremost Clock-flow Graph , traversing of clocks to the complete Chip. List of all the clocks,Generated Clocks with frequencies. Clocks with number of sinks, This is just an extra input for the CTS designer to know the amount of sink and just to have a feel what could be the achieved insertion delay targets.
- Incase if the chip has some Macros or 3 rd Party Hard I.P's, what is the achieved clock-tree targets like the achieved insertion delays, skew numbers within that Macro.This information is needed while the CTS person builds the tree from the Chip level.
- What are the balance points incase if there are some special requirements, based on the design requirements to say that the clocks has to reach at the so and so places at the specific skew difference.
- List of the Clock -Muxes where two different clocks are coming and ending at the Muxes. This information is needed whether there should be kept break-points at the inputs of these muxes.
- Knowledge about the Clock groups say clock A, clock B and clock C are one domain and there skew are important and need to be controlled whereas Clock D , clock E , clock F are of different groups, within the group there is some requirement for skews where as across the groups there is no relation ship and there is no concern of strict skew targets to be achieved.
- What is the acceptable local skew and global skew targets.
- In case of some designs where in the memory macros will have strict requirement on hold , so the memory clocks will be pulled few odd ps say 100 or 150 ps early than the other clocks to reduce their hold violation, in case if there is any information which needs to be honoured need to be communicated to the CTS designer.
- There could be some designs where in the Data flops (say 16 or 32 in number) need to meet specific skew targets, need to be specified.
- Information about the PLL's , which generates what clocks, to know from where the clock tree need to be start to built.
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