- Study says that Clock sub-system's consumes typically almost 30% of the energy in the Chip, so gating the clock to reduce useless transitions.
- As Energy E = Switching* Capacitance * Sqr(Voltage), the clock-gating technique, reduces the switching factor, So clock-gating plays a major role in Dynamic power reduction.
Clock-gating Concepts Synchronous Logic implementation with out Clock-gating (fig 1) Synchronous Logic implementation with Clock-gating (fig 2) 
-diagram Courtesy Atrenta Clock-gating Issues & Design practices - Power aware clock-gating cell insertion as adding more number of clock-gating cells increases area, creates routing congestion, creates Clock tree synthesis challenges.
For example:Location of ICG(Integrated clock Gating) cells 
-courtesy Synopsys - DFT challenges like how the clocks will behave during test-mode, Steps to by-pass during test-modes, so the flip-flop's get clocks.
-courtesy Synopsys 
-courtesy Synopsys - Glitch-free clock-gating cells. Latch based clock gate cells prevent glitch on the enable from being propagated to the gated clock circuitary.
-courtesy Synopsys - Multi-level clock-gating to save maximum amount of power(The first level of clock-gating is done at the chip-level usually controlled throught software, second level is at the module level using FSM, the third level is right near by the flip-flop level.
-courtesy Analog Devices.
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