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what do I need to look for in the design, to meet Timing Qualification/Closure 1. Perform check design/model.
2. check how many flops are not with clocks.
3. check for any timing loop in the design
4. check whether all the Ports are constrained for input/output delays
5. Check whether all the clock-gating checks are performed.
6. Is the clock skews/clock insertions are in the limit , rather it is in the acceptable targets.
7. Did the design has setup/hold uncertainities mentioned for jitter and so on and meets timing requirements.
8. Is the Design functionaly fine in a Multi mode Design Environment
9. Is the Design meets asynchronous checks like recovery/removal.
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