In this article let us think over what are various parameters to be looked in to for an optimal System bus architecture in an SoC, in order to have maximum performance possible. - System speed is not only dependant on the Processor/Micro-controller but also on the Bus speed the system operates.
- Contention Prevention mechanism's across multiple drivers.
- Bus Splitters: Hierarchical Bus structures, based on the speed targets {for example the AMBA bus from ARM, has two bus hierarchy levels : Advanced High Performance Bus[AHB] & Advanced Peripheral Bus[APB]. Split bus architectures has energy efficient transactions and concurrent data transactions over the conventional buses.
- Reducing latency and crossbar utilization mechanisms.
- Optimum Bridging Mechanisms for cross data Transfer's among the Buses.
- Performance Enhancers by having Pipeline mechanism's and steps to prevent Stalling.
- Arbitration Protocol schemes for shared buses {Fixed Priority Schemes, Round Robin Scheme, Time Division Multiplexing Schemes}.
- Mechanisms to reduce bus waiting time.
- Synchronization mechanism's across the bus
- Scheduling based on power-profiling.
- Traffic based Dynamic Voltage and frequency scaling techniques for meeting power-targets.
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