|
Synthesis is a step of mapping the RTL files (verilog format or vhdl format) to convert it to the technology specific cells..
Prerequisites To perform synthesis.
1. RTL files
2. Synopsys constraints file, Design constraints file, explaining the priorities of cost functions like area/timing/power
3. Technology specific library files.
Synthesis Reference flow
Featured Articles related to this topic
Explains about the timing paths and how to time in a design
|
Comments