what to look for when  i  get a 3rd party I.P.

• Chip design is a very complex integration Process, where in we cannot afford to master in every part of the chip designing process why? : Time constraint. so we do work with lot of 3 rd party I.P.[Intellectual property].
• while some one delivers us an I.P. what all to look for? just a few thoughts/experiences shared dear designers.

• have you been delivered with the electrical specification and is the I.P. timing characteristics in-lined with the standard/protocol timing requirement, if an I.P. deals with specific standards.
• Does the I.P. comes with enough documentation like, Clock Flow Graph, Data flow Graph, integration guidelines, Clock tree guidelines (like insertion/skew), Timing guidelines,Integration guidelines
• In DFT guidelines
  • number of scan-chains,
  • whether lockup latches are part of the chain
  • Whether clock mixes have happenned
  • what is the length of the scan-chain
  • what are the memories present, in which what all memories has BIST[Built in Self Test] implemented.
  • What is the ATPG coverage numbers
  • What is the redundancy added to the memories.
  • Is there any negative flops part of the chain.
  • what is the length of the EDT chain
  • what is the length of by-pass chain
• In Integration Guidelines
  • Explanation of Ports and it is basic functionality and port directions.
  • What are all clock,reset,scan ports.
• clock-Tree Guidelines
  • Detailed Clock flow graph
  • what is the achieved latency/skew/frequency numbers.
  • Some basic information about clocks like number of sinks.
• Timing Guidelines
  • What is the operating frequency , what is the achieved frequency
  • Is timing constraints file part of the delivery
  • Is the macro has the timing library characterized for all the ports.
  • Is there timing models available.
  • Do we have timing reports (setup/hold/transition/capacitance) for all possible modes(functional/scan/mbist/boundaryscan/bypass/EDT) for slow/fast corners.
  • Does clock-gating checks performed
  • what are all static clock gating and what are dynamic clock gating stuffs
  • did timing verified for Signal integrity enabled, if so what are all the filter settings used and is it aligned with the process.
  • did timing verified including on-chip variation enabled, if so what is the derate variation applied for setup and hold timing checks.
  • if some violations are waived off , available waivers list and reasoning behind the waivers.
  • is check-timing report available to know the quality of timing constraints used like all the flip-flops getting clocks, all the ports are constrained, and things like-that.
  • what is the uncertainity numbers used for setup and hold checks for timing closure.
• Integration Guidelines
  • What are the metals used for power-grid
  • what are the metals used for clock-tree
  • is routing over memory performed
  • did routing performed with SI enabled or not.
  • Information about the power structure like rails/straps/ring structures and the grid used in the macro.
  • what is the utilization, flop count, gate count, what is the square mm.
  • Does your 3 rd I.P comes with pads , what is the pad pitch .
  • what is the I.R. drop numbers for the macro
  • what is the total power numbers