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VLSI Frequently Asked Interview Questions & Answers


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1. what is the difference between mealy and moore state-machines

In the mealy state machine we can calculate the next state and output both from the input and state. But in the moore state machine we can calculate only next state but not output
from the input and state and the output is issued according to next state.

2. How to solve setup & Hold violations in the design

To solve setup violation

1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx]
3. Tweak launch-flop to have better slew at the clock pin, this
will make CK->Q of launch flop to be fast there by helping fixing
setup violations
4. Play with skew [ tweak clock network delay, slow-down clock to
capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews)
To solve Hold Violations

1. Adding delay/buffer[as buffer offers lesser delay, we go for spl
Delay cells whose functionality Y=A, but with more delay]
2. Making the launch flop clock reaching delayed

3. Also, one can add lockup-latches [in cases where the hold time
requirement is very huge, basically to avoid data slip]

3. What is antenna Violation & ways to prevent it

During the process of plasma etching, charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. IF a small transistor gate connected to these long metal strips, the gate oxide can be destroyed (large electric field over a very thin electric) , This is called as Antenna violation.

The ways to prevent is , by making jogging the metal line, which is atleast one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we are etching metal2, metal3 layer is not laid out. So the two
pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge to gate. When we laydown metal3, the remaining portion of metal got charge added to metal3. This is called
accumulative antenna effect.
Another way of preventing is adding reverse Diodes at the gates


FAQ continued on page 2

 

Frequently Asked Questions with Answers in our FAQ Bank Account

what is the difference between mealy and moore state-machines

How to solve setup & Hold violations in the design

What is antenna Violation & ways to prevent it

We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage?


what is tie-high and tie-low cells and where it is used

what is the difference between latches and flip-flops based designs

What is High-Vt and Low-Vt cells.

What is LEF mean?

what is DEF mean?

Steps involved in designing an optimal padring

What is metastability and steps to prevent it.

what is local-skew, global-skew,useful-skew mean?

What are the various timing-paths which i should take care in my STA runs?

What are the various components of Leakage-power?

What are the various yield-losses in the design?

what is meant by virtual clock definition and why do i need it?

What are the various Variations which impacts timing of the design?

What are the various Design constraints used while performing Synthesis for a design?

Specify few verilog constructs which are not supported by the synthesis tool.

Vds-Ids curve for an MOSFET, with increasing Vgs.

Basic Operation of an MOSFET.

What is Channel length Modulation?

what is body effect?

What is latchup in CMOS design and ways to prevent it?

What are the various design changes you do to meet design power targets?

what is meant by Library Characterizing:

what is meant by wireload model:

what are the measures to be taken to design for optimized area

what all will you be thinking while performing floorplan

what are the measures in the Design taken for Meeting Signal-integrity targets

what are the measures or precautions to be taken in the Design when the chip has both analog and digital portions

what are the steps incorporated for Engineering Change Order[ECO]

what are the steps performed to achieve Lithography friendly Design

what does synthesis mean

Explain the Synthesis flow

What are the various ways to reduce Clock Insertion Delay in the Design

what are the various functional verification methodologies

3What does formal verification mean?


How will you time the output paths?


How will you time the input paths?


what is false path mean in STA and in what scenarios falsepath can come?


what do you call an event and when do you call an assertion,?


what does Multicycle path mean in STA and in what scenarios multicycle paths can come?


what are source synchronous paths in STA?


assume you have defined latency specified by user both in Master clock and in the Generated clock in STA, how the tool will behave any idea?


Assume there is a specific requirement to preserve the logic during synthesis, how will do it.


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